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| AB-2061G-33 33Mhz PCI to Local Bus Interface for 8 or 16 bit Local Bus Applications 32- to 16- bit PCI to local bus translator AB-2061-33 33Mhz PCI to Local Bus Interface Product Specification AB Semicon AB-2061-33 32 bit to 8 or 16 bit PCI to local bus translator Product Specification Copyright (c) Copyright 1997 AB Semicon Limited. All rights reserved. No part of this publication may be reproduced, transmitted, transcribed, stored in a retrieval system, or translated into any language or any computer language, in any form or by any third party, without the prior written permission of AB Semicon Limited. Disclaimer AB Semicon Limited reserves the right to revise this publication and to make changes from time to time to the contents hereof without obligation to notify any person or organization of such revision or changes. AB Semicon Limited has endeavoured to ensure that the information in this publication is correct, but will not accept liability for any error or omission. - 2 - rev 1.2 AB-2061-33 33Mhz PCI to Local Bus Interface Features: * * High speed 33Mhz Ideal for interfacing 32-bit PCI bus to 8 or 16-bit local bus systems Mailbox (Door Bell) and Interrupt 100-pin PQFP package Low Power C-Mos Technology 0.6micron Byte aligned transfers Enhanced interprocessor handshaking * * * * * rev 1.2 - 3 - Introduction The AB-2061 device described in this document is intended to support a subset of the PCI bus specification. However this does not preclude the use of this device on standard PCI buses, as the electrical specifications are the same and the minimum feature set is supported. The device contains a number of shared registers for interprocessor communication and mechanisms for generating interrupts to the PCI and local buses. The device supports the transfer of blocks in a way which reduces load on the local processor and also makes efficient use of the PCI bus by maintaining sensible size bursts and reducing the number of single data phase transactions to a minimum. In order to decouple the relative speed differences between the two buses, the device incorporates a pair of FIFOs - First In First Out memory buffers, one for each direction. Each FIFO can hold four 32-bit words. There is no direct access to the local memory space provided by this device, and the PCI side cannot set up DMA transfers which are solely under the control of the local processor. Communication between buses is via the 32 byte shared register block or the mailbox registers. AB-2061-33 has a 3.3v PCI bus interface which will operate at a maximum frequency of 33MHz. The local processor bus can be run at either 3.3 or 5v depending upon the power supply. - 4 - rev 1.2 Chip Structure Local Control Local Signals Address Local Data LD(7:0) LD(15:0) Local Slave Sequencer Local Datapath 32 Mailbox Reg 32 Shared Register Register Arbiter DMA Registers PCI Config. Registers FIFO 1 32x4 FIFO FIFO 2 32x4 FIFO DMA Control PCI Master/ Slave Sequencers PCI Data Path PCI Control Signals Figure 1 Functional Block Diagram PAD(31:0) CBE(3:0) rev 1.2 - 5 - Applications The chip can be used in many different applications where interfacing to a peripheral device such as a printer or a scanner is required. The device can be used to connect two processor systems and their respective buses with a high speed interface so that there is no degradation in processing time on either side of the systems by allowing fully asynchronous access from both sides of the system. Figure 2 gives an overview of low-cost yet high-speed network interface applications for which this chip is suitable. EXAMPLE for a Network Interface Card Figure 3 shows a Network Interface with a bus connector to interface to a printer controller board. NIC Card Figure 2 Printer Controller Board PCI BUS 1:33Mhz PCI PCI PCI PCI Bus I/O Slot 2061-33 Local BUS CPU RAM ROM Network Interface Card Figure 3 - 6 - rev 1.2 Pin-Out for AB-2061-33 The following diagram shows the pin-out for the AB-2061-33 PCI to local bus interface chip: s D D1 s D3 s s s s s s s E3 E1 E s s s Index corner Pin 1 b s rev 1.2 - 7 - s s s s e Packaging Information s s s s s s c s s 0 = 07 A A2 s Symbol Control Dimensions Alternative Dimensions in millimetres in inches MIN Nominal MAX MIN Nominal MAX A 2.80 3.40 0.110 0.134 A1 0.25 0.85 0.010 0.033 A2 2.55 3.05 0.100 0.120 D 23.65 24.15 0.931 0.951 D1 19.80 20.20 0.780 0.795 D3 18.85 REF. 0.742 REF. E 17.65 18.15 0.695 0.715 E1 13.80 14.20 0.543 0.559 E3 12.35 REF. 0.486 REF. L 0.73 1.03 0.029 0.041 e 0.65 BSC. 0.026 BSC. b 0.22 0.38 0.009 0.015 c 0.11 0.23 0.004 0.009 Pin features N 100 ND 30 NE 20 NOTE RECTANGULAR Conforms to JEDEC MO-112 CC-1 Iss. B. Note: This package is rectangular - 8 - rev 1.2 G D s s s A1 0.1 L s Functional Description of Signals PCI Signals PIN Name PAD(31:0) GNT/REQ CBE(3:0) PRST INTA IRDY/TRDY DEVSEL IDSEL SERR/PERR FRAME STOP PAR PCLK Local Bus Signals LD(16:0) RD / R/W WR / E CS ALE BHE LA(3:0) LINT MODE(2:0) WAIT Data Bus Read Strobe / Data direction Write Strobe / Data Strobe Chip Select Address Latch Byte Enable for 16 bit bus Address Bus Local Interrupt Local Bus Mode Local Wait Signal 16 (8) 1 1 1 1 1 4 1 3 1 Function Multiplexed Address/Data Bus Arbitration Command/Byte Enables Reset Interrupt Initiator/Target Ready Device Select Initialisation Select Error Reporting Cycle start/running Stop Transaction Parity PCI Bus Clock Number of Pins 32 2 4 1 1 2 1 1 2 1 1 1 1 Total Active Signals : 80 - 16 Bit bus 72 - 8 Bit bus rev 1.2 - 9 - On Chip Resources Configuration Registers The PCI specification requires a minimum set of configuration registers, taking up some 64 bytes. These registers are accessible from the PCI bus via configuration cycles, though not all are writable. The local processor also requires access to the configuration registers in order to set them up with the correct values. These registers are specified fully in the PCI Rev 2.1 Documentation. Shared Register Block The chip contains a block of registers 32 bytes in length. These are accessible via PCI from the address held in the configuration register, Base Address 0 via normal read/write cycles. Again the local processor also has access to these registers. One of these holds the offset register which contains pointers to various on-chip resources. DMA Control The DMA controller transfers data in both directions between the card local memory and the peripheral memory, although only the local processor will need to coordinate the transfers and be able to see the DMA control registers. Using DMA in this manner makes it easier to transfer data on the PCI bus in bursts, and hence decrease the amount of bus bandwidth taken up by the card. This could be important for certain types of device which may not work if the PCI bus is heavily loaded. A size of 16 bytes (4 long words) is ideal. Due to the potential difference in clock speeds and bandwidths between the local PCI buses, FIFOs are necessary to allow this. The controller allows one transfer of non-longword aligned blocks by the use of the DMA_MASK register. Mailbox Registers There are two mailbox registers for interprocessor communications which generate interrupts to the relevant processor when read from or written to. These interrupts are individually maskable. - 10 - rev 1.2 Accessing On Chip Registers Most registers in the device are not directly accessible; an indirect scheme is used whereby the internal address of the register required is written to a REGISTER_ADDRESS register and data transferred to and from the register via the REGISTER_DATAn port. Some registers are directly accessible for reasons of speed. The chip appears to the local processor to be a set of 16 8-bit ports starting at some system-defined base address. These are: Address Name Base Offset 0 REGISTER_ADDRESS Function Indirect address register, holds the address of the register to be accessed through REGISTER_DATA0..3 1 RESOURCE_STATUS (R) Read : Returns status of DMA and FIFOs RESOURCE_CONTROL (W) Write : DMA/PCI control bits FIFO_DATA0 FIFO_DATA1 (16 bit only) REGISTER_DATA0 REGISTER_DATA1 REGISTER_DATA2 REGISTER_DATA3 Read : Data from PCI through FIFO1 Write : Data to PCI through FIFO2 Byte 0 of indirectly accessed register Byte 1 of indirectly accessed register Byte 2 of indirectly accessed register Byte 3 of indirectly accessed register 2 3 4 5 6 7 rev 1.2 - 11 - RESOURCE_CONTROL Register Bit 0 1 Name DMA1_ENABLE DMA1_PAUSE Function When set to 1 DMA channel #1 will start. Writing a 0 will stop and reset the channel. Writing a 1 will cause DMA on channel #1 to pause until a 0 is written when it will recommence. When set to 1 DMA channel #2 will start Writing a 0 will stop and reset the channel. Writing a 1 will cause DMA on channel #2 to pause until a 0 is written when it will recommence. Setting this bit to a 1 will allow the PCI bus controller to perform bursts of less than four long words. Used to flush last bytes from the FIFO. When set to 1 some registers in the shared register block are write protected. When 1 all PCI bus accesses to the shared register block will be terminated with RETRY. Set to 0 after reset. When 0 all PCI configuration cycles will be terminated with RETRY. Writing 1 will allow configuration cycles to proceed normally. Set to 0 after a reset. 2 DMA2_ENABLE 3 DMA2_PAUSE 4 FIFO2-FLUSH 5 6 PROTECT_REGISTERS LOCK_REGISTERS 7 CONFIG_ENABLE - 12 - rev 1.2 RESOURCE_STATUS Register Bit 0 Name DMA1_COMPLETE Function A 1 indicates that the last word in a block has been placed into FIFO 1 by DMA channel #1. A 1 indicates that DMA CHANNEL #2 has transferred the last word in a block to PCI memory space. PCI > Local FIFO is empty. Local > PCI FIFO is full. Unrecoverable error during a transfer on channel 1. Unrecoverable error during a transfer on channel 2. Undefined. Undefined. 1 DMA2_COMPLETE 2 3 4 5 6 7 FIFO1_EMPTY FIFO2_FULL DMA1_ERROR DMA2_ERROR SPARE SPARE rev 1.2 - 13 - PCI Configuration Registers These are accessed by the local processor through an indirect method using REGISTER_ADDRESS and REGISTER_DATAn. The PCI uses configuration cycles to get at these. PCI Config. Addr. 0 2 4 6 8 9 A B C D E F 10 14 18 1C 20 24 28 2C 2E 30 34 38 3C 3D 3E 3F Local Name Indirect Addr. 0(0,1) Vendor ID 0(3,2) 1(0,1) 1(3,2) 2(0) 2(1) 2(2) 2(3) 3(0) 3(1) 3(2) 3(3) 4(3-0) 5(3-0) 6(3-0) 7(3-0) 8(3-0) 9(3-0) A(3-0) B(0,1) B(3,2) C(3-0) D(3-0) E(3-0) F(0) F(1) F(2) F(3) Device ID Command Status Revision ID Interface Register Sub Class Code Base Class Code Cache Line Size Latency Timer Header Type BIST Base Address 0 Base Address 1 Base Address 2 Base Address 3 Base Address 4 Base Address 5 Cardbus CIS Pointer Subsystem ID Subsystem Vendor ID ROM Base Address Reserved Reserved Interrupt Line Interrupt Pin Min Grant Max Latency Width Function Default Va l u e 16 16 16 16 8 8 8 8 8 8 8 8 32 32 32 32 32 32 32 16 16 32 32 32 8 8 8 8 Interface Device Manufacturer ID code Interface Device ID code PCI Command register PCI Status register Interface Device Revision Contains index to chip's offset register PCI Sub Class code PCI Base Class code NOT IMPLEMENTED Maximum burst duration 00h or 80h NOT IMPLEMENTED Base addr. of card resources NOT IMPLEMENTED NOT IMPLEMENTED NOT IMPLEMENTED NOT IMPLEMENTED NOT IMPLEMENTED NOT IMPLEMENTED Vendor assigned card ID no. Card Manufacturer ID code NOT IMPLEMENTED NOT IMPLEMENTED NOT IMPLEMENTED Interrupt line routing Interrupt Pin NOT IMPLEMENTED PCI Maximum Latency 1309h 080Dh 0000h 0200h 00h 18h 80h FFh 00h 00h 00h 00h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h 0000h 0000h 00000000h 00000000h 00000000h 00h 00h 00h 00h Only the upper 20 bits of Base Address 0 are writable, giving an address range of 4k. This cannot be changed from either the local or PCI bus. Local addresses are given as the indirect address to be written to REGISTER_ADDRESS followed by the byte number(s) i.e. the Vendor ID can be accessed by writing 0 to REGISTER_ADDRESS and then reading or writing REGISTER_DATA0 and REGISTER_DATA1. - 14 - rev 1.2 Shared Register Block These are accessed by the local processor through an indirect method using REGISTER_ADDRESS and REGISTER_DATAn. The PCI uses memory accesses and BaseAddress0 to locate these registers. PCI Local Name Addr. Indirect Addr. 0 10(1,0) LPG0 2 10(3,2) LPG1 4 6 8 A C E 10 12 14 15 16 17 18 1C 11(1,0) 11(3,2) 12(1,0) 12(3,2) 13(1,0) 13(3,2) 14(1,0) 14(3,2) 15(0) 15(1) 15(2) 15(3) 16(3-0) 17(3-0) LPG2 LPG3 LPG4 Reserved BD0 PG0 PG1 PG2 PG3 BD1 PG4 Reserved PG5 PG6 Width Function (Interprocessor Communication Register) Default Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 30343800h 00000000h 16 16 16 16 16 16 16 16 16 16 8 8 8 8 32 32 Interprocessor Communication Register " " " " DO NOT USE " " " " " " " DO NOT USE " " " " " " " " " " " " " " " " " " " " " " " " " " " " Note: PG4, PG3, PG5, PG6 & BDI are write protected when the PROTECT_REGISTERS bit in RESOURCE_CONTROL is set. LPGn writable by the local processor PGn writable by the PCI BDn writable by either local or PCI All shared registers are readable by either the local processor or the PCI bus. rev 1.2 - 15 - DMA Control Registers These can only be accessed by the local processor through an indirect method. Local Indirect Addr. 18(3-0) 19(1,0) 19(3,2) 1A(3-0) 1B(1,0) 1B(1,0) 24(0) 24(1) Name DMA1_SOURCE_BASE DMA1_LENGTH DMA1_DEST_BASE DMA2_DEST_BASE DMA2_LENGTH DMA2_SOURCE_BASE DMA_MASK RESOURCE_CONF Width Function 32 16 16 32 16 16 8 8 Base address of DMA transfers from PCI > Local Length in long words of PCI > Local DMA NOT IMPLEMENTED Base address of DMA transfers from Local > PCI Length in long words of Local > PCI DMA NOT IMPLEMENTED Byte masks for first and last word in DMA transfers Bit 0 = local FIFO endian mode (see section on DMA controller units) Interrupt Control Registers PCI Local Name Address Indirect Address 30 1C(3-0) INTERRUPT_SET 34 38 1D(3-0) 1E(3-0) INTERRUPT_CLEAR INTERRUPT_STATUS Width Function 32 32 32 Written to by PCI to assert LINT Written by local to assert PCI #INTA. Written to by the PCI to clear PCI INTA#. Written by local processor to clear LINT. Non zero to PCI when card is asserting INTA#. Non zero to Local when card is asserting Local INT. The values written to INTERRUPT_SET and INTERRUPT_CLEAR are irrelevant. Mailbox Registers These registers are located in the memory space of PCI, addresses given are offsets from the base address assigned to the chip. Local access is through the indirect addressing, using the REGISTER_ADDRESS and REGISTER_DATA0..3 ports. PCI Addr. Indirect Local Addr. 40h 44h 48h 4Ch 70h 74h 20h(3-0) 21h(3-0) 22h(3-0) 23h(3-0) 2Ch(3-0) 2Dh(3-0) Name Printer Control Register (PCR) Printer Status Register (PSR) Device Control Register (DCR) Device Status Register (DSR) Printer Handshake Register (PHR) Device Handshake Register (DHR) Width 32 32 32 32 32 32 Default Value 00000000h 00000000h 00000000h 00000000h 00000000h 00000000h - 16 - rev 1.2 Printer Control Register 40h (20h) Bit 28 27 26 25 24 POR Local PCI Access Value Access 0 0 0 0 0 RD RD RD RD RD RD/WR RD/WR RD/WR RD/WR RD/WR Function 1 1 1 1 1 = = = = = Enable PCI interrupt on local write to DHR Enable PCI interrupt on local read from PHR Enable PCI interrupt on Target Abort Enable PCI interrupt on Master Abort Software Reset - Generates local interrupt if enabled Printer Status Register 44h (21h) Bit 28 27 26 25 POR/RST Value 0 0 0 0 Local PCI Access Access RD RD RD RD RD/WR RD/WR RD RD Function When When When When read, read, read, read, 1 1 1 1 = = = = Local has written to DHR, Write 1 to clear Local has read from PHR, Write 1 to clear Target Abort has occurred Master Abort has occurred Device Control Register 48h (22h) Bit 28 27 26 25 24 POR Value 0 0 0 0 0 Local Access RD/WR RD/WR RD/WR RD/WR RD/WR PCI Access RD RD RD RD RD Function 1 1 1 1 1 = = = = = Enable Enable Enable Enable Enable local local local local local interrupt on PCI write to PHR interrupt on PCI read from DHR interrupt on Target Abort interrupt on Master Abort interrupt on Software Reset Device Status Register 4Ch (23h) Bit 28 27 26 25 24 POR/RST Value 0 0 0 0 0 Local Access RD/WR RD/WR RD RD RD PCI Access RD RD RD RD RD Function When When When When When read, read, read, read, read, 1 1 1 1 1 = = = = = PCI has written to PHR, Write 1 to clear PCI has read from DHR, Write 1 to clear Target Abort has occurred Master Abort has occurred PCI has set the software rev 1.2 - 17 - Printer Handshake Register 70h (2Ch) This is the mailbox used to pass data from PCI to local. When a PCI write to the PHR occurs an interrupt to the local processor is generated. When the local processor reads the register an interrupt to PCI is generated (the interrupt is actually generated when byte 3 is read, so the local processor should follow the usual convention of reading that byte last). Each interrupt is individually maskable. Device Handshake Register 74h (2Dh) This mailbox is used to pass data from local to PCI. When a local write to the DHR occurs an interrupt to PCI is generated (again, always write byte 3 last). When PCI reads the DHR an interrupt to the local processor is generated. Each interrupt is individually maskable. - 18 - rev 1.2 I/O Pin Assignment Pin ID 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Signal LA<1> LA<0> Designator Local Address Bus 1 Local Address Bus 2 Vss Vdd (5v) RD WR ALE BHE CS MODE<2> MODE<1> MODE<0> LD<15> LD<14> LD<13> LD<12> LD<11> LD<10> LD<9> LD<8> LD<7> LD<6> LD<5> LD<4> LD<3> Read Strobe Write Strobe Address Latch Upper Byte Enable (16 bit bus) Chip Select Local Bus Mode 2 Local Bus Mode 1 Local Bus Mode 0 Local Data 15 Local Data14 Local Data13 Local Data12 Local Data11 Local Data10 Local Data 9 Local Data 8 Local Data 7 Local Data 6 Local Data 5 Local Data 4 Local Data 3 rev 1.2 - 19 - I/O Pin Assignment Pin ID Signal Designator 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LD<2> LD<1> Local Data 2 Local Data 1 Vdd (5v) LD<0> LWAIT LINT Local Data 0 Wait (Local) Interrupt (Local) Vss PRST PCLK GNT REQ PAD<31> PAD<30> PAD<29> Reset PCI Bus Clock Bus Arbitration - Grant Bus Arbitration - Request PCI Address and Data 31 PCI Address and Data 30 PCI Address and Data 29 VssAC PAD<28> PCI Address and Data 28 VssDC VddDC (3v) PAD<27> PAD<26> PAD<25> PAD<24> CBE<3> IDSEL PAD<23> PCI Address and Data 27 PCI Address and Data 26 PCI Address and Data 25 PCI Address and Data 24 Command/Byte Enable 3 Initialisation Select PCI Address and Data 23 - 20 - rev 1.2 I/O Pin Assignment Pin ID 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Signal PAD<22> Designator PCI Address and Data 22 VssAC VssDC PAD<21> PAD<20> PAD<19> PAD<18> PAD<17> PCI Address and Data 21 PCI Address and Data 20 PCI Address and Data 19 PCI Address and Data 18 PCI Address and Data 17 VddDC (3v) PAD<16> PCI Address and Data 16 VddAC (3v) CBE<2> FRAME IRDY TRDY DEVSEL STOP INTA Command/Byte Enable 2 Cycle Start Initiator Ready Target Ready Device Select Stop Transaction PCI Interrupt VddAC (3v) VssAC PERR Parity Error VssDC VddDC (3v) SERR PAR System Error Parity rev 1.2 - 21 - I/O Pin Assignment Pin ID 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 PAD<5> PAD<4> PAD<3> PAD<2> PAD<1> PAD<0> DMARREQ DMAWREQ LA<2> PAD<6> PAD<14> PAD<13> PAD<12> PAD<11> PAD<10> PAD<9> PAD<8> CBE<0> PAD<7> Signal CBE<1> PAD<15> Designator Command/Byte Enable 1 PCI Address and Data 15 VddDC (3v) PCI Address and Data 14 PCI Address and Data 13 PCI Address and Data 12 PCI Address and Data 11 PCI Address and Data 10 PCI Address and Data 9 PCI Address and Data 8 Command/Byte Enable 0 PCI Address and Data 7 VssDC PCI Address and Data 6 VssAC VddAC (3v) PCI Address and Data 5 PCI Address and Data 4 PCI Address and Data 3 PCI Address and Data 2 PCI Address and Data 1 PCI Address and Data 0 DMA Read Request DMA Write Request Local Address Bus 2 To minimise noise on output pins it is advisable to ensure a degree of isolation between the AC (noisy) power supply and the DC (quiet) supply pins. i.e. they should be connected to power planes using separate vias'. - 22 - rev 1.2 Z80 Type Read Trdd Z80 Type Write Trsu Tasu Tcsh Tah Trcr Twd TIon TIoff Twds Twdh Trdd Chip select setup time to read/write strobe asserted Address setup time to read/write strobe asserted Chip select hold time from read/write strobe deasserted Address hold from chip select deasserted Recovery time to next assertion of chip select Time to assert WAIT from chip select Data out turnon time from read strobe asserted Data out turnoff time from read strobe deasserted Write data setup time Write data hold time Read data valid from WAIT deasserted rev 1.2 - 23 - 6502 Type Read Trdd 6502 Type Write Trsu Tasu Tcsh Tah Trcr Twd TIon TIoff Twds Twdh Trdd Chip select setup time to read/write strobe asserted Address setup time to read/write strobe asserted Chip select hold time from read/write strobe deasserted Address hold from chip select deasserted Recovery time to next assertion of chip select Time to assert WAIT from chip select Data out turnon time from read strobe asserted Data out turnoff time from read strobe deasserted Write data setup time Write data hold time Read data valid from WAIT deasserted - 24 - rev 1.2 Multiplexed Bus Mode AD(3:0) ALE ADDR. Tapw Tmas Tmah Tapw Tmas Tmah ALE Pulse Width Multiplexed address setup Multiplexed address hold rev 1.2 - 25 - Local Bus Controller Unit The Local Bus Controller Unit (LBCU) sequences all the operations necessary to transfer data to and from the microprocessor, both in slave mode (register accesses) and master mode (DMA transfers). The LBCU is made up of three units, the Local Slave Sequencer Unit (LSSU), the Local Data Path Unit (LDPU) and the Local Master Sequencer Unit (LMSU). (In AB-2061 the LMSU is not present or active). The LSSU handles all transactions when the microprocessor is driving the local bus; these transactions are exclusively register accesses. When the DMA unit requires to transfer data from the local memory to the onchip FIFOs or vice versa, it signals the LMSU which obtains control of the local bus using the BUSREQ and BUSGNT lines, and then sequences the spitting or assembly of 32 bit words for transfer over 8 or 16 bits. (Only in local bus mastering capable variants). The LDPU is the collection of multiplexers required to split or assemble the bytes/ words and long words. Local Bus Configuration Local bus configuration is determined at reset by the levels on the MODE[2:0] pins. The value on these pins MUST NOT change outside the period where PRST is asserted. Mode 0 1 2 =1 6502 Type strobes - E, R/W Non multiplexed bus 8 bit data =0 Z80 Type strobes - RD, WR Multiplexed bus 16 bit data - 26 - rev 1.2 DMA Controller Units The DMA Controller units (DCUs) contain the control logic, pointers and counters to schedule, sequence and provide source and destination addresses for data passing through the FIFOs. These units ensure that the maximum burst length possible is always used. In the case of AB2061 this is 4 longwords (32 bytes). DMA transfers can be byte aligned within the PCI memory space, operation of this feature is described in the DMA_MASK section. AB2061 is not capable of directly placing data into a memory on the local bus. The job of retrieving data from and writing data to the FIFOs is up to the local processor or some other DMA capable device. FIFO access has been specially optimised to allow transfer to local memory by relatively simple DMA controllers such as those present on many microcontroller devices. Initialising DMA Transfers DMA Channel 1 always moves data from the PCI memory space to the FIFOs and hence into the local memory. Channel 2 moves data from local memory into PCI memory space. Channel1: DMA1_SOURCE_BASE Holds a 32 bit address. This is the first location in the PCI memory space of the block to be copied to local memory. DMA1_LENGTH This 16 bit register holds the length in longwords of the block to be copied to local memory. Holds a 32 bit address. This is the first location in the PCI memory space of the block where data from local memory will be placed A 16 bit value which specifies the length of the transfer in longwords. This 8 bit value determines which bytes are written in the first and last words of the block, thus allowing blocks to be byte aligned. Channel2: DMA2_DEST_BASE DMA2_LENGTH DMA_MASK rev 1.2 - 27 - DMA Status The RESOURCE_STATUS register contains bits that allow the local processor to monitor the progress or otherwise of ongoing DMA transfers. DMA1_COMPLETE The last word of data has been placed in FIFO1 by DMA channel 1. This DOES NOT however indicate that the data is in local memory yet. (See FIFO1_EMPTY) DMA2_COMPLETE DMA Channel2 has moved the last word from FIFO2 into the PCI memory space. FIFO1_EMPTY FIFO1 (PCI to LOCAL) is empty of data. If there is more data expected, the local processor must wait until this flag is reset. If DMA1_COMPLETE and FIFO1_EMPTY are both set the program can assume the whole block has now been fetched. FIFO2 (LOCAL to PCI) if full and no more data should be written into it. FIFO2_FULL DMA1_ERROR DMA2_ERROR These flags indicate that an attempt to read or write the PCI memory space failed for an non-recoverable reason. AB2061 regards PCI Master Abort (no device responds) and PCI Target Abort events as non-recoverable. Starting, Stopping and Resetting DMA In order to get either DMA channel to re-read its BASE and LENGTH registers, the appropriate ENABLE bit MUST be written as a '0'. To start a channel write the BASE and LENGTH values, write a '0' to the ENABLE bit, followed immediately by a '1'. Writing a 1 to a channel that is already running will not disturb its operation in any way. To stop a channel in operation, write '0' to the appropriate ENABLE bit. Note that this will STOP and RESET the channel. In order to pause without resetting the counters and pointers write a '1' to the appropriate PAUSE bit. The pause function will not stop a burst in progress once AB2061 has asserted REQuest to the PCI bus. DMA Channel 2 will normally only try to initiate a burst on the PCI bus when FIFO2 is full (4 longwords). In cases where this is undesirable such as a block of - 28 - rev 1.2 3 or less longwords are left, the FIFO2_FLUSH bit must be set. This bit allows DMA2 to initiate a burst with any quantity of data in FIFO2. Do not forget to reset this bit after completion of the block transfer as it can dramatically reduce the transfer speed and bus efficiency of AB2061. NEVER attempt to reset the CONFIG_ENABLE bit in the RESOURCE_CONTROL register when any DMA is running. Doing so causes AB2061 to enter a factory test mode and will cause unpredictable PCI memory space corruption. Reading and Writing Data DMA data is read from and written to the FIFO_DATA register. This is either a 8 or 16 bit port depending on the data bus width. In 8 bit mode four sucessive reads will retrieve one full 32 bit word from FIFO1 and 4 writes will place one 32 bit word into FIFO2. The order that the bytes are written to and retrieved from the fifos is determined by the ENDIAN bit in the RESOURCE_CONFIG register. In 16 bit mode FIFO_DATA must be read and written as a 16 bit wide port, two reads/writes are required per 32 bit word. As an example, assume the top word of FIFO1 contains the value 00C0FFEEh. In 8 bit mode with ENDIAN=0 four reads of FIFO_DATA return EE, FF, C0, 00 ENDIAN=1 four reads of FIFO_DATA return 00, C0, FF, EE In 16 bit mode with ENDIAN=0 two reads of FIFO_DATA return FFEE, 00C0 ENDIAN=1 two reads of FIFO_DATA return 00C0, FFEE Writing data to FIFO2 follows the same ordering convention. The internal 'byte/word pointers' for this function are reset when a '0' is written to the associated channel's DMA_ENABLE bit. Local bus DMAC signals AB2061 has a DMA request pin for each channel, this allows a simple twochannel DMAC on the local bus to read and write the fifos without CPU intervention. DMARREQ - Active low and asserted when FIFO1 contains data DMAWREQ - Active low and asserted when FIFO2 has space for data rev 1.2 - 29 - Non Aligned DMA Transfers AB2061 supports the transfer of non word aligned blocks from the local processor to PCI. Non aligned transfers from PCI to local are not supported however. This feature is implemented through the DMA_MASK register which is 8 bits wide. The lower nibble determines the pattern output on the PCI byte enables when writing the first word of a block (and hence which bytes are written). The upper nibble has the same effect on the last word of the block. Example: To write the block shown below, the DMA_MASK register should be written with the value 38h. 1) 2) 3) 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 Byte 3 2 1 0 0 = Byte written DMA_MASK Bit: 0 7 0 6 1 5 1 4 1 3 0 2 0 1 0 0 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 109876543210987654321 Shading indicates bytes to be transferred Notes It is possible to write non contiguous data with this feature, however this is strongly discouraged and may result in some targets signalling a system error on SERR. When the local processor is writing data to the FIFO, it must always write to FIFO_PCI_DATA4 last, regardless of whether that byte will be written in the word. Failure to do this will result in the loss of the entire word of data. When performing transfers of one word (or less), the upper and lower nibbles of the DMA_MASK register should be written to the same value. Electrical Specification VDD_3 VDD_5 Icu GND and GNDc Input - Low Input - High Output - Low Output - High Input - Load +3.3V 10% +5.0V 10% +3.3V 10% 20mA (typ) 40mA (max) 0V < 0.7V > 1.8V < 0.6V > 2.6V 5pF Operating Temperature: Range 0C - 70C Humidity 90% (Non condensing) Storage Temperature: Range -10C - +80C Humidity 95% (Non condensing) Product has to be used within 6-7 hours after unpacking. Distributed in Japan Rikei Corporation 1-26-2 Nishi-Shinjuku Shinjuku-Ku Tokyo 163-05 Japan Tel: +81 3 3345 2189 Fax: +81 3 3344 3949 AB Semicon Limited AB Semicon House 62 Victoria Road Burgess Hill West Sussex RH15 9LH Tel: +44 (0) 1444 870408 Fax: +44 (0) 1444 870452 |
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